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ISL6410, ISL6410A
Data Sheet September 17, 2004 FN9149.3
Single Synchronous Buck Regulators with Integrated FET
The ISL6410, ISL6410A are synchronous current-mode PWM regulators designed to provide a total DC-DC solution for microcontrollers, microprocessors, CPLDs, FPGAs, core processors/BBP/MAC, and ASICs. The ISL6410 should be selected for applications using 3.3V 10% as an input voltage and the ISL6410A in applications requiring 5.0V 10%. These synchronous current mode PWM regulators have integrated N- and P-Channel power MOSFETs and provide pre-set pin programmable outputs. Synchronous rectification with internal MOSFETs is used to achieve higher efficiency and a reduced external component count. The operating frequency of 750kHz typical allows the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. A power good signal "PG" is generated when the output voltage falls outside the regulation limits. Other features include overcurrent protection and thermal overload shutdown. The ISL6410, ISL6410A are available in an MSOP 10 lead package.
Features
* Fully Integrated Synchronous Buck Regulator * PWM Fixed Output Voltage Options - 1.8V, 1.5V or 1.2V with ISL6410 (VIN = 3.3V) - 3.3V, 1.8V or 1.2V with ISL6410A (VIN = 5.0V) * Continuous Output Current . . . . . . . . . . . . . . . . . . 600mA * Ultra-Compact DC-DC Converter Design * Stable with Small Ceramic Output Capacitors * High Conversion Efficiency * Extensive Circuit Protection and Monitoring features - Overvoltage, UVLO - Overcurrent - Thermal Shutdown * Available in MSOP and QFN packages * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Packaging Available
Ordering Information
PART NUMBER* ISL6410IR ISL6410IRZ (Note) ISL6410IU ISL6410IUZ (Note) ISL6410AIR ISL6410AIRZ (Note) ISL6410AIU ISL6410AIUZ (Note) TEMP. RANGE (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 16 Ld 4x4 QFN 16 Ld 4x4 QFN (Pb-free) 10 Ld MSOP 16 Ld 4x4 QFN 16 Ld 4x4 QFN (Pb-free) 10 Ld MSOP PKG. DWG. # L16.4x4 L16.4x4 M10.118 L16.4x4 L16.4x4 M10.118
Applications
* CPUs, DSP, CPLDs, FPGAs * ASICs * DVD and DSL applications * WLAN Cards * Generic 5V to 3.3V Conversion
10 Ld MSOP (Pb-free) M10.118
Pinouts
ISL6410 (MSOP) TOP VIEW
PVCC VIN GND PG FB 1 2 3 4 5 10 PGND 9 8 7 6 L EN SYNC VSET VIN CT GND PG 1 2 3 4 5 FB 6 NC 7 VSET 8 PG
ISL6410 (QFN) TOP VIEW
PGND 13 12 NC 11 RESET 10 EN 9 SYNC PVCC 15 VIN
10 Ld MSOP (Pb-free) M10.118
L 14
*For tape and reel, add "-T", "-TK" or "-T5K" suffix. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
16
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram for MSOP Version
VIN 10F PVCC 1 0.1F
2
VIN
CURRENT SENSE SOFT START SLOPE COMPENSATION EN EA GM PWM OVERCURRENT, OVERVOLTAGE LOGIC L 9
2
3
GND
L1 8.2H GATE DRIVE
VOUT
10F COMPENSATION PGND 7 SYNC 750kHz OSCILLATOR 10
ISL6410, ISL6410A
6
VSET
POWER GOOD PWM VOUT
UVLO
8
EN
PWM REFERENCE 0.45V FB 4 PG 5
NOTES: 1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A. 2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.
Functional Block Diagram for QFN Version
VIN 10F PVCC 15 0.1F
16 VIN
CURRENT SENSE SOFT START SLOPE COMPENSATION EN EA GM PWM OVERCURRENT, OVERVOLTAGE LOGIC L 14
3
3
GND
L1 8.2H GATE DRIVE
VOUT
10F COMPENSATION PGND 9 SYNC 750kHz OSCILLATOR 13
ISL6410, ISL6410A
7
VSET
POWER GOOD PWM VOUT
UVLO
VIN 11 RESET BLOCK RESET
10 EN
PWM REFERENCE 0.45V FB 4 PG 8 PG 2C T 5
NOTES: 1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A. 2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.
ISL6410, ISL6410A Typical Application Schematics
VIN 3.3V 10% CIN 10F
0.1F
1 PVCC 2 VIN
PGND 10 L9
L1 8.2H VOUT 1.8V COUT 10F
ISL6410
3 GND 4 PG 5 FB
EN 8 SYNC 7 VSET 6
FIGURE 1. SCHEMATIC USING THE ISL6410 MSOP
VIN 5.0V 10%
CIN 10F
0.1F
1 PVCC 2 VIN
PGND 10 L9
L1 12H VOUT 3.3V COUT 10F
ISL6410A
3 GND 4 PG 5 FB
EN 8 SYNC 7 VSET 6
FIGURE 2. SCHEMATIC USING THE ISL6410A MSOP
+3.3V VIN VIN PVCC L PGND CIN 10F GND 1F 1 2 3 16 15 14 13 12 11
L1 8.2H COUT 10F NC
+1.2V VOUT
VIN
GND
VSET
C7 0.1F
CT 0.01F
NC
PG
CT RESET U1 10 GND ISL6410IR EN 9 4 PG SYNC 17 EP FB 5 6 7 8 RESET BAR
FIGURE 3. SCHEMATIC USING THE ISL6410 QFN
4
ISL6410, ISL6410A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V SYNC, FB, VSET & Enable Input (Note 3) . . . . -0.3V to VCC+0.3V ESD Classification (Human Body Model) . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) MSOP Package (Note 4) . . . . . . . . . . . 128 NA QFN Package (Notes 4, 5). . . . . . . . . . 45 7.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (10s, soldering . . . . . . . . . . . . . 260C Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . -40C to 85C Junction Temperature Range. . . . . . . . . . . . . . . . . . . -40C to 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. All voltages are with respect to GND. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY Supply Voltage Range
Recommended operating conditions unless otherwise noted. VIN = 3.3V 10% (ISL6410) or 5V 10% (ISL6410A), TA = 25C (Note 6). TEST CONDITIONS MIN TYP MAX UNITS
VIN (ISL6410) VIN (ISL6410A)
3.0 4.5 2.62 2.53 4.27 4.1 -
3.3 5.0 2.68 2.59 4.37 4.22 2.3 5 10 150 20
3.6 5.5 2.73 2.64 4.45 4.32 10 15 25
V V V V V V mA A A C C
Input UVLO Threshold
VTR (ISL6410) Rising VTF (ISL6410) Falling VTR (ISL6410A) Rising VTF (ISL6410A) Falling
Quiescent Supply Current Shutdown Supply Current
IOUT = 0mA EN = GND, TA = 25C EN = GND, TA = 85C
Thermal Shutdown Temperature (Note 7) Thermal Shutdown Hysteresis (Note 7) SYNCHRONOUS BUCK PWM REGULATOR Output Voltage
Rising Threshold
ISL6410, VSET = L ISL6410, VSET = H ISL6410, VSET = OPEN ISL6410A, VSET = L ISL6410A, VSET = H ISL6410A, VSET = OPEN
-1.5 -0.5 -1.5 700
1.2 1.8 1.5 1.2 3.3 1.8 230 230 92
+1.5 +0.5 +1.5 600 1300 -
V V V V V V % % % mA mA m m %
Output Voltage Accuracy Line Regulation Load Regulation Maximum Output Current Peak Output Current Limit PMOS rDS(ON) NMOS rDS(ON) Efficiency
IOUT = 3mA, TA = -40C to 85C IOUT = 3mA IOUT = 3mA to 600mA
IOUT = 200mA IOUT = 200mA IOUT = 200mA, VIN = 3.3V, VO = 1.8V (ISL6410)
-
5
ISL6410, ISL6410A
Electrical Specifications
PARAMETER Efficiency Efficiency Soft-Start Time OSCILLATOR Oscillator Frequency Frequency Synchronization Range (fSYNC) SYNC High Level Input Voltage SYNC Low Level Input Voltage Sync Input Leakage Current Duty Cycle of External Clock Signal (Note 7) PGOOD (ISL6410 interfaces to 3.3V Logic, ISL6410A interfaces to 5.0V Logic) Rising Threshold Falling Threshold Rising/Falling Hysteresis ENABLE EN High Level Input Voltage EN Low Level Input Voltage EN Input Leakage Current OVERVOLTAGE Overvoltage Threshold RESET BLOCK SPECIFICATIONS RESET (reset released) RESET (reset asserted) RESET Rising Threshold RESET Falling Threshold RESET (reset released) RESET (reset asserted) RESET Rising Threshold RESET Falling Threshold RESET Threshold Hysteresis RESET Threshold Hysteresis RESET Active Timeout Period (Note 8) VSET VSET High Level Input VSET Low Level Input VSET Open Level Input VIN-0.4V VIN /2 0.4 V V V ISL6410, ISOURCE = 500A, VIN = 2.90V ISL6410, ISINK = 1.2mA, VIN = 2.50V ISL6410 ISL6410 ISL6410A, ISOURCE = 800A, VIN = 4.70V ISL6410A, ISINK = 3.2mA, VIN = 4.10V ISL6410A ISL6410A ISL6410 ISL6410A CT = 0.01mF 0.8VIN 2.74 2.72 0.8VIN 4.5 4.47 2.78 2.77 4.58 4.55 20 30 25 0.3 2.81 2.79 0.4 4.64 4.61 V V V V V V V V mV mV ms 27 30 33 % As % of VIN As % of VIN EN = GND or VIN 70 -1 30 1 % % A 1mA minimum source/sink +5.0 -10.5 8.0 -8.0 1 +10.5 -5.0 % % % Clock signal on SYNC pin As % of VIN As % of VIN SYNC = GND or VIN 620 500 70 -1 20 750 860 1000 30 1 60 kHz kHz % % A % Recommended operating conditions unless otherwise noted. VIN = 3.3V 10% (ISL6410) or 5V 10% (ISL6410A), TA = 25C (Note 6). (Continued) TEST CONDITIONS IOUT = 200mA, VIN = 5.0V, VO = 3.3V (ISL6410A) IOUT = 600mA, VIN = 5.0V, VO = 3.3V (ISL6410A) 4096 Clock Cycles @ 750kHz MIN TYP 93 91 5.5 MAX UNITS % % ms
NOTES: 6. Specifications at -40C and +85C are guaranteed by design, not production tested. 7. Guaranteed by design, not production tested. 8. The RESET Timeout period is linear with CT at a slope of 2.5ms/nF, thus a 10nF capacitor provides for 25ms.
6
ISL6410, ISL6410A Pin Description
VIN - Supply voltage for the IC. It is recommended to place a 1F decoupling capacitor as close as possible to the IC. GND - Small signal ground for the PWM controller stage. All internal control circuits are referenced to this pin. PG - The Power good is an open-drain output. A pull-up resistor should be connected between PG and VIN. It is asserted active high when the output voltage reaches 94.5% of the nominal value. FB - The Feedback pin is used to sense the output voltage, and should be connected to VOUT for normal operation. VSET - This pin is used to program the output voltages. Refer to Table 1 below for details.
TABLE 1. VSET High Open (NC) Low ISL6410 Vo 1.8V 1.5V 1.2V ISL6410A Vo 3.3V 1.8V 1.2V
efficiency and reduced number of external components. Operating frequency of 750kHz typical allows the use of small inductor and capacitor values. The device can be synchronized to an external clock signal in the range of 500kHz to 1MHz. The PG output indicates loss of regulation on PWM output. The PWM is based on the peak current mode control topology with internal slope compensation. At the beginning of each clock cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via an internal circuit. On exceeding a preset limit the high side switch is turned off causing the PWM comparator to trip. This occurs whenever the output voltage is in regulation or when the inductor current reaches the current limit. After a minimum dead time to prevent shoot through current, the low side N-channel MOSFET turns on and the current ramps down. As the clock cycle is completed, the low side switch turns off and the next clock cycle is initiated. The control loop is internally compensated thus reducing the amount of external components. The switch current is internally sensed and the maximum current limit is 1300mA peak.
SYNC - This pin is used for synchronization. The converter switching frequency can be synchronized to an external CMOS clock signal in the range of (500kHz to 1MHz). EN - A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current to less than 10A at 25C. This pin should be pulled up to VCC via a 10K resistor. L - This pin is the drain junction of the internal power MOSFETs and is to be connected to the external inductor. PGND - Power ground. Connect all power grounds to this pin. PVCC - This pin provides the Input supply for the internal MOSFETs. It is recommended to place a 1F decoupling capacitor as close as possible to the IC. CT - Timing capacitor connection to set the 25ms minimum pulse width for the RESET signal. RESET - The outputs of the reset supervisory circuit, which monitors VIN. The IC asserts these RESET signals whenever the supply voltage drops below a preset threshold and keeps it asserted for at least 25ms after VCC (VIN) has risen above the reset threshold. These outputs are pushpull. RESET is LOW when re-setting the microprocessor. The PWM will continue to operate until VIN drops below the UVLO threshold.
Synchronization
The typical operating frequency for the converter is 750kHz. It is possible to synchronize the converter to an external clock frequency in the range of 500kHz to 1000kHz when an external signal is applied to SYNC pin. The device will automatically detect and synchronize to the rising edge of the first clock pulse. If the clock signal is stopped, the converter automatically switches back to the internal clock and continues its operation without interruption. The switch over will be initiated if no rising edge triggers are present on the SYNC pin for a duration of four clock cycles.
Soft-Start
As the EN (Enable) pin goes high, the soft-start function will generate an internal voltage ramp. This causes the start-up current to slowly rise preventing output voltage overshoot and high inrush currents. The soft-start duration is typically 5.5ms with 750kHz switching frequency. When the soft-start is completed, the error amplifier will be connected directly to the internal voltage reference.
Enable
Logic low on EN pin forces the PWM section into shutdown. In the shutdown mode all the major blocks of the PWM including power switches, drivers, voltage reference, and oscillator are turned off.
Functional Description
The ISL6410, ISL6410A is a synchronous buck regulator with integrated N- and P-channel power MOSFET and provides pre-set pin programmable outputs. Synchronous rectification with internal MOSFETs is used to achieve higher
Undervoltage Lockout
An undervoltage lockout circuit prevents the converter from turning on when the voltage on VIN is less than the values specified in the Input UVLO Threshold section of the electrical specification.
7
ISL6410, ISL6410A
Power Good
This output is asserted high when the PWM is enabled, and Vout is within 8.0% typical of its final value, and is active low outside this range. When disabled, the output turns active low. It is recommended to leave the PG pin unconnected when not used.
Input Capacitor Selection
The input current to the buck converter is pulsed, and therefore a low ESR input capacitor is required. This results in good input voltage filtering and minimizes the interference it causes to other circuits. The input capacitor should have a minimum value of 10F and a higher value can be selected for improving input voltage filtering. The input capacitor should be rated for the maximum input ripple current calculated as:
Vo Vo I RMS = Io ( max ) x -------- x 1 - -------- Vin Vin
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM cycle, exceeding the overcurrent limit, causes a 4 bit up/down counter to increment by one LSB. A normal current state causes the counter to decrement by one LSB (the counter will not however "rollover" or count below 0000). When the PWM goes into overcurrent, the counter rapidly reaches count 1111 and the PWM output is shut down and the soft-start counter is reset. After 16 clocks the PWM output is enabled and the soft-start cycle is started. If Vout exceeds the overvoltage limit for 32 consecutive clock cycles the PWM output is shut off and the soft-start cycle is initiated.
The worst case RMS ripple current occurs at D = 0.5 and is calculated as: Irms = Io/2. D = Duty Cycle Ceramic capacitors are preferred because of their low ESR value. They are also less sensitive to voltage transients when compared to tantalum capacitors. It is good practice to place the input capacitor as close as possible to the input pin of the IC for optimum performance.
No Load Operation
If there is no load connected to the output, the converter will regulate the output voltage by allowing the inductor current to reverse for a short period of time.
Inductor Selection
The ISL6410 is an internally compensated device and hence a minimum of 8.2H must be used for the ISL6410 and a minimum of 12H for the ISL6410A. The selected inductor must have a low DC resistance and a saturation current greater than the maximum inductor current value can be calculated from the equations below
Vo 1 - -------Vin dIL = Vo x -----------------Lxf IL max = Io max + dIL -------2
Output Capacitor Selection
For best performance, a low ESR output capacitor is needed. Output voltages below 1.8V require a larger output capacitor and ESR value to improve the performance and stability of the converter. For 1.8V output applications, a ceramic capacitor of 10F or higher value with ESR 50m is recommended. The RMS ripple current is calculated as:
Vo 1 - -------Vin 1 ------------------ x ---------------I RMS ( Co ) = Vo x Lxf 2x 3
where dIL = the peak to peak inductor current L = the inductor value f = the switching frequency ILmax = the max inductor current
TABLE 3. RECOMMENDED INDUCTORS INDUCTOR VALUE 8.2H 12H DCR (m) 75 100 COMPONENT SUPPLIER Coilcraft MSS6122-822MX Coilcraft MSS6122-123MX
L = the inductor value f = the switching frequency The overall output ripple voltage is the sum of the voltage spike caused by the output capacitor ESR and the voltage ripple caused by charge and discharge of the output capacitor:
Vo 1 - -------Vin 1 Vo = Vo x ------------------ x ------------------------ + ESR 8 x Co x f Lxf
Where the highest output voltage ripple occurs at the highest input voltage VIN.
TABLE 2. RECOMMENDED OUTPUT CAPACITORS CAPACITOR VALUE 10F ESR (m) COMPONENT SUPPLIER COMMENTS Ceramic
<50 AVX 08056D106KAT2A
8
ISL6410, ISL6410A
Layout Considerations
As in all switching power supplies, the layout is an important step in the design process, more so at high peak currents and switching frequencies. Improper layout practice will give rise to Stability and EMI issues. It is recommended that wide and short traces are used for the main current paths. The input capacitor should be placed as close as possible to the IC pins. This applies to the output inductor and capacitor as well. The analog ground, GND, and the power ground, PGND, need to be separated. Use a common ground node to minimize the effects of ground noise.
Performance Curves and Waveforms
100 VOUT = 1.8V 90 EFFICIENCY (%) IOUT = 200mA VOUT = 1.5V VOUT = 1.2V EFFICIENCY (%) 90 IOUT = 600mA 100
80
80
70
70
60
60
50
50
100 IOUT LOAD CURRENT (mA)
1000
50
2.9
3.1 3.3 VIN INPUT VOLTAGE (V)
3.5
FIGURE 4. ISL6410 EFFICIENCY vs LOAD CURRENT
FIGURE 5. ISL6410 VIN vs EFFICIENCY
100 VOUT = 3.3V 90 EFFICIENCY (%) VOUT = 1.8V EFFICIENCY (%)
100 IOUT = 200mA 90 IOUT = 600mA
80
VOUT = 1.2V
80
70
70
60
60
50 50
100 IOUT LOAD CURRENT (mA)
1000
50 4.4
4.6
4.8
5.0 VIN (V)
5.2
5.4
5.6
FIGURE 6. ISL6410A EFFICIENCY vs LOAD CURRENT
FIGURE 7. ISL6410A EFFICIENCY vs VIN
9
ISL6410, ISL6410A Performance Curves and Waveforms
800 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) -15
(Continued)
780
790
770
780
760
770
750
760
740
750 -40
10 35 TEMPERATURE (C)
60
85
730 -40
-15
10 35 TEMPERATURE (C)
60
85
FIGURE 8. ISL6410 OSCILLATOR FREQUENCY vs TEMPERATURE CH1 = Top, CH2 = Middle, CH4 = Bottom, where applicable
FIGURE 9. ISL6410A OSCILLATOR FREQUENCY vs TEMPERATURE
VOUT
VOUT
L PIN VOLTAGE
L PIN VOLTAGE
L1 CURRENT
L1 CURRENT
VIN = 5.0V, VOUT = 1.2V, IOUT = 0.5A 0.5s/DIV CH1 = 0.1V/DIV, CH2 = 2V/DIV CH4 = 200mA/DIV 0.5s/DIV CH1 = 0.1V/DIV, CH2 = 2V/DIV CH4 = 200mA/DIV
FIGURE 10. SWITCHING WAVEFORM FOR ISL6410
FIGURE 11. SWITCHING WAVEFORM FOR ISL6410A
VOUT
VOUT
IOUT
IOUT
VIN = 3.3V, VOUT = 1.2V 0.5ms/DIV CH1 = 0.2V/DIV, CH4 = 200mA/DIV
VIN = 5.0V, VOUT = 1.2V 0.5ms/DIV CH1 = 0.1V/DIV, CH4 = 200mA/DIV
FIGURE 12. TRANSIENT LOAD WAVEFORM FOR ISL6410
FIGURE 13. TRANSIENT LOAD WAVEFORM FOR ISL6410A
10
ISL6410, ISL6410A Performance Curves and Waveforms
(Continued)
VOUT
VOUT
VIN = 3.3V, VOUT = 1.2V 1s/DIV CH1 = 20mV/DIV
VIN = 5.0V, VOUT = 1.2V 1s/DIV CH1 = 20mV/DIV
FIGURE 14. RIPPLE WAVEFORM FOR ISL6410
FIGURE 15. RIPPLE WAVEFORM FOR ISL6410A
-40 VIN = 3.3V, VOUT = 1.2V -50 -60 -70 -80 -90 -100 -110 -120
-40 VIN = 5.0V, VOUT = 1.2V -50 -60 -70 -80 -90 -100 -110 -120 NOISE LEVEL 761kHz = -54.0dBm CENTER 2.75MHz, SPAN = 4.5MHz NOISE LEVEL 732kHz = -65.3dBm CENTER 2.75MHz, SPAN = 4.5MHz
FIGURE 16. SWITCHING HARMONICS AND NOISE FOR ISL6410
FIGURE 17. SWITCHING HARMONICS AND NOISE FOR ISL6410A
11
ISL6410, ISL6410A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
12
ISL6410, ISL6410A Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
4X L L1
e E L
0.020 BSC 0.187 0.016 0.199 0.028
0.50 BSC 4.75 0.40 5.05 0.70
A
A2
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 10 0.003 0.003 5o 0o 15o 6o
0.95 REF 10 0.07 0.07 5o 0o
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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